This invention generally relates to semiconductor memory devices and technology, and in particular to negative differential resistance (NDR) elements and static random access memory (SRAM) devices that utilize the same.
A new type of FET and SRAM device using the same (NDR FETs) is described in detail in a patent application Ser. No. 10/029,077 filed Dec. 21, 2001 assigned to the present assignee, and published on May 9, 2002 as Publication No. 2002/0054502. The NDR FET structure, operation and method of making the same are discussed in detail in patent application Ser. No. 09/603,101 filed Jun. 22, 2000 by King et al, which is also assigned to the present assignee. Such details are also disclosed in a corresponding PCT application PCT/US01/19825 which was published as publication no. WO 01/99153 on Dec. 27, 2001. The above materials are hereby incorporated by reference.
As is well known, soft errors in memory devices are caused by, among other things, cosmic rays (neutrons), and alpha particles present in semiconductor materials and packaging. In typical SRAMs, the failure rate attributable to soft-errors (the so-called soft-error ratexe2x80x94SER) is measured by a metric known as Failures In Time (FIT); the basic unit of this benchmark refers to a malfunction occurrence frequency, where 1 FIT represents one malfunction every one billion hours (approximately 100,000 years) per device. For a conventional SRAM operating under normal conditions an FIT value of up to several thousand is considered adequate, and a value of less than approximately 1000 FIT/Mbit is preferable for embedded memory applications. In some applications more stringent requirements may be needed (i.e, on the order of 10-100 FIT/Mbit).
Soft errors can also influence SRAM embodiments which use NDR devices. Thus there is clearly a need for NDR FET and an NDR FET based SRAM device that have superior soft error characteristics.
An object of the present invention is to provide a memory device such as a static random access memory (SRAM) cell which utilizes NDR FETs, and which has improved soft error rate (SER) performance.
A first aspect of the invention concerns a method of forming a semiconductor field effect transistor (FEI) for a memory device, the FET having a control gate, a source region, and a drain region. This method includes generally the following steps: forming a channel for carrying a current between the source and drain regions; and forming a trapping layer located proximate to and forming an interface with the channel. The trapping layer includes trapping sites adapted for trapping at least warm carriers from the channel so as to effectuate a negative differential resistance mode for the FET. To tailor characteristics of the FET, including an operational switching speed for the FET, the trapping sites are also tailored. In other words, the FET speed is directly related to a distance which the trapping sites are located from the interface, such that locating the trapping sites at a distance D1 results in a maximum operational switching speed S1, and such that locating the trapping sites at a distance D2 (D2 greater than D1) results in a minimum operational switching speed S2 (S2 less than S1). Thus, the trapping sites are distributed within the trapping layer at an approximate distance D (D2 greater than D greater than D1) in accordance with a target operational switching speed S for the FET (S1 greater than S greater than S2) and a target soft error rate for the memory device.
The trapping sites are distributed at a particular distance by adjustment of an implant energy and dosage, and/or a thermal anneal operation. In a preferred embodiment, D1 is about 0.5 nm, and D2 is about 1.0 nm. Preferably no traps are included in the bulk of the trapping layer that forms a gate dielectric for the NDR FET. The operational speed of the FET is thus between about 10 nanoseconds and 1 picosecond using contemporary conventional technology. This also achieves a soft error rate of less than about 1000 failures in time per Mbit.
In other variations, an additional set of trapping sites are formed at an approximate distance Dxe2x80x2 from the interface where (D2 greater than Dxe2x80x2 greater than D1).
To prevent them from achieving a high concentration in a bulk region, a rapid thermal anneal (RTA) is performed after such implant. Alternatively the trapping layer can be formed by two distinct layers, including a first dielectric layer and a second dielectric layer, where the trapping sites are located only, within the first dielectric layer.
In yet another variation, the trapping sites are located laterally along only a limited portion or region near the interface. Preferably this limited portion is nearer the source than the drain of the NDR capable FET.
Another aspect of the invention concerns a memory device which uses a trap layer in which charge traps are used to effectuate NDR characteristics for the load and driver elements. The charge traps are distributed in the trap layer so as to cause the memory cell to achieve a soft error rate of approximately 1,000 failures-in-time (FITs)/Mbit or less.
In a preferred embodiment, the memory device is a static random access memory (SRAM) cell, and the load and driver elements are both NDR-capable FETs. The charge traps are distributed in the trap layer so that the NDR-capable FETs switch with a switching speed between 1 picosecond and 10 nanoseconds.
Other particular aspects of the invention pertain to the character of the traps, such as their material properties (preferably a doping impurity such as Boron), their density (preferably about 1 to 5*1014 traps/cm2 at a distance of about 0.5 nm from an interface of the trapping layer with a channel of the NDR-capable FET) their energy (preferably about 0.5 eV above a conduction band edge of a channel of the NDR-capable FET), and methods for forming the same within a memory cell.